14.23 TagLo (28) and TagHi (29) Registers
PTag0: contains physical address bits [35:12] stored in the cache tag
PState: contains the primary instruction cache state for the line, as follows:
1 = Valid
0 = Invalid
LRU: indicates which way is the least recently used of the set. (See page 256 in Errata.)
TP: tag even parity bit.
PTag1: contains physical address bits [39:36] stored in the cache tag
Figure 14-28 shows the fields of the TagHi and TagLo registers.
Figure 14-28 TagHi/Lo Register Fields in Primary Instruction Cache
When CacheOp is Index Load/Store Tag
0: Reserved. Must be written as zeroes, and returns zeroes when read. (See page 224 of Errata.)
State Modifier: holds the status of the line, as follows:
0012 = neither refilled or written
0102 = this line may have been written and inconsistent from the secondary cache (W bit)
1002 = this line is being refilled (Refill bit).
PTag1: contains physical address bits [39:36] stored in the cache tag
PTag0: contains physical address bits [35:12] stored in the cache tag
PState: together with the Refill bit of the State Modifier in the TagHi register, PState determines the state of the cache block in the primary data cache, as shown in Table 14-24.
Table 14-24 PState Field Definition in TagHi/Lo Registers, For Primary Data Cache Operation
When CacheOp is Index Load/Store Tag
LRU: indicates which way is the least recently used of the set. (See page 257 in Errata.)
Way: indicates which secondary cache set contains the primary cache line for this tag
TP: tag even parity bit.
0: Reserved. Must be written as zeroes, and returns zeroes when read. (See page 224 of Errata.)
Figure 14-29 TagHi/Lo Register Fields in Primary Data Cache
When CacheOp is Index Load/Store Tag
STag0: contains physical address bits [35:18] stored in the cache tag
SState: contains the secondary cache state of the line, as follows:
002 = Invalid
012 = Shared
102 = Clean Exclusive
112 = Dirty Exclusive
VIndex (virtual index): contains only two bits of significance since the32 Kbyte 2-way set associative primary caches are addressed using only two untranslated address bits (VA[13:12]) plus the offset within the virtual page.
ECC: contains the ECC for the STag, SState and VIndex fields.
MRU: indicates which way was the most recently used in the set (See page 258 in Errata.)
0: Reserved. Must be written as zeroes, and returns zeroes when read. (See page 224 of Errata.)
Figure 14-30 TagHi/Lo Register Fields in Secondary Cache
When CacheOp is Index Load/Store Tag
Figure 14-30, STag0 field. (See page 258 of Errata.).
